XTREMEDSP DESIGN CONSIDERATIONS
Xilinx • 51
P => P, -- 48-bit product output
PCOUT => PCOUT, -- 38-bit cascade output
A => A, -- 18-bit A data input
B => B, -- 18-bit B data input
BCIN => BCIN, -- 18-bit B cascade input
C => C, -- 48-bit cascade input
CARRYIN => CARRYIN, -- Carry input signal
CARRYINSEL => CARRYINSEL, -- 2-bit carry input select
CEA => CEA, -- A data clock enable input
CEB => CEB, -- B data clock enable input
CEC => CEC, -- C data clock enable input
CECARRYIN => CECARRYIN, -- CARRYIN clock enable input
CECINSUB => CECINSUB, -- CINSUB clock enable input
CECTRL => CECTRL, -- Clock Enable input for CTRL registers
CEM => CEM, -- Clock Enable input for multiplier
registers
CEP => CEP, -- Clock Enable input for P registers
CLK => CLK, -- Clock input
OPMODE => OPMODE, -- 7-bit operation mode input
PCIN => PCIN, -- 48-bit PCIN input
RSTA => RSTA, -- Reset input for A pipeline registers
RSTB => RSTB, -- Reset input for B pipeline registers
RSTC => RSTC, -- Reset input for C pipeline registers
RSTCARRYIN => RSTCARRYIN, -- Reset input for CARRYIN registers
RSTCTRL => RSTCTRL, -- Reset input for CTRL registers
RSTM => RSTM, -- Reset input for multiplier registers
RSTP => RSTP, -- Reset input for P pipeline registers
SUBTRACT => SUBTRACT -- SUBTRACT input
);
-- End of DSP48_inst instantiation
Verilog Instantiation Template
The following is a synthesis instantiation template for the DSP48 slice in Verilog. After the port list
are synthesis attributes with syntax written for the Xilinx Synthesis Tool (XST). If using a different
synthesis tool, consult the tools user guide and change the attributes appropriately. The section after
the synthesis attributes consists of “
defparam” statements that are ignored by the synthesis process,
but are used to initialize the simulation model to match the synthesis attributes during simulation.
// DSP48 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (DSP48_inst) and/or the port declarations within the
// code : parenthesis maybe changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.
// <-----Cut code below this line---->
// DSP48: DSP Function Block
// Virtex-4
// Xilinx HDL Language Template version 7.1i
DSP48 DSP48_inst (
.BCOUT(BCOUT), // 18-bit B cascade output
.P(P), // 48-bit product output
.PCOUT(PCOUT), // 38-bit cascade output
.A(A), // 18-bit A data input
.B(B), // 18-bit B data input
.BCIN(BCIN), // 18-bit B cascade input
.C(C), // 48-bit cascade input
.CARRYIN(CARRYIN), // Carry input signal
.CARRYINSEL(CARRYINSEL), // 2-bit carry input select
.CEA(CEA), // A data clock enable input